Differential non-linearity correction scheme

ABSTRACT

Differential non-linearity errors in an A/D converter are corrected by an analog system. The system produces different analog voltages which are used to correct the input voltage to the capacitor. The input voltage is changed by an amount which is effective to correct the CΔV to be the same as it would have been if the DNL error had not occurred.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.09/739,932, filed Dec. 18, 2000, which is a continuation of U.S.application Ser. No. 09/170,944, filed Oct. 13, 1998, which claims thebenefit of the U.S. Provisional Application Nos. 60/062,854, filed onOct. 14, 1997.

FIELD

[0002] The present specification describes a technique of correcting fordifferential non-linearity in an A/D converter.

BACKGROUND

[0003] Certain A/D converters, including a successive approximation A/Dconverter, operate based on calibrated capacitors.

[0004] A plurality of capacitors are provided. Each capacitor has acapacitance that is related to the other capacitors according to powersof 2. Hence, the capacitors produce an output charge where eachrepresents one bit of the final digital signal. The A/D converter usesthese capacitors to estimate the digital signal that it will produce.

[0005] The estimation includes changing each bit between a 1 and 0,which effectively changes the connection to each capacitor. FIG. 1 showsthe connection to each capacitor C1, C2, C3, being switched between twovoltages: the source voltage VDD and ground. The switching is based onwhether the bit associated with that capacitor is 1 or 0. The number ofswitches and number of capacitors hence corresponds to the number ofbits, with one capacitor being associated with one bit.

[0006] The output of the capacitor string is used by the A/D converter100 to produce its output 102. The output 102 depends, upon otherthings, on the accuracy of the capacitors and their scaling.

[0007] As described above, each capacitor has a capacitance value whichshould be equal to a basic capacitance value C_(x)x2^(n), where n+1 isthe number of bits of resolution of the A to D converter.

[0008] Even though the capacitors are scaled relative to one another,there are often errors in the scaling. A differential non-linearity canoccur based on errors in the relationship of the sizes and capacities ofthe capacitors. The mechanisms and causes of differentialnon-linearities are well known in the art.

[0009] The differential non-linearities cause certain codes in theoutput of the A/D converter to be missing. This effectively reduces thedynamic range of the A/D converter, causes granularity, and also may beperceived as noise. It is desirable to correct the differentialnon-linearity.

[0010] It has been suggested to correct a differential non-linearity byusing a look-up table for each value. This, however, requires a lot ofmemory.

[0011] A co-pending and commonly-assigned application suggestscorrecting the differential non-linearity by assigning a correctionvalue to each active bit.

[0012] The present specification teaches a different solution to solvingdifferential non-linearity problems. This is done by adjusting an analogvoltage which is placed on the capacitor. Hence, the previous-knownsolutions require a digital correction.

[0013] According to the preferred mode, the operation is corrected bychanging the bias voltage that is applied to the capacitors. In theprior art, each of the capacitors C1, C2, . . . CN, receives the samevoltage: typically the rail voltage VDD. According to this system, atleast a number of the capacitors receive customized voltages which aredifferent than the rail voltage. These voltages are customized tocorrect for the differential non-linearity error caused by errors inscaling of the values of the capacitors.

[0014] In a first preferred mode, the corrected voltages are produced bydigital-to-analog converters which are driven by a memory storingcorrection values.

[0015] Another alternative which is completely analog uses a variableresistor or resistor ladder to do this.

DESCRIPTION OF THE DRAWINGS

[0016] These and other aspects will now be described in detail withreference to the accompanying drawings, wherein:

[0017]FIG. 1 shows a prior art system of operating A/D converter using acapacitor bank;

[0018]FIG. 2 shows a first embodiment using a biased capacitor bank tooperate an A/D converter;

[0019]FIG. 3 shows a third embodiment using an all analog system with apotentiometer to operate the A/D converter bank; and

[0020]FIG. 4 shows a fourth embodiment using a resistor ladder.

DESCRIPTION OF THE EMBODIMENTS

[0021]FIG. 2 shows a preferred embodiment of the compensation system.The output charge on the line 200, which is connected to the A/Dconverter 100, is proportional to the voltage on the capacitors and thevalues of the capacitors. The capacitors in FIG. 2 are scaled similarlyto those in FIG. 1: where a value of each capacitorC_(n)=C_(x)·2^(n)+offset_(n), where n ranges from 0 to the number oftotal bits-1. The offsets_(n) represents the differential non-linearityfor the specific bit, which represents the undesired effect.

[0022] The output charge on the line 200 drives the A/D converter andprovides a reference for determining whether the current estimate of theA/D converter is correct. According to this embodiment, an active node202 of the capacitor is connected to a voltage which differs from VDD byan amount which compensates for the error in capacitance value. All orjust some of the capacitors can be compensated in this way. If only someof the capacitors are corrected, it is preferably the ones correspondingto the most significant bits.

[0023] Assuming FIG. 2 is to represent a three-bit A/D converter, thecharge on the line 200 can be expressed as follows.

Q=(C _(x) +DNL ₁)·ΔV ₁+(2C _(x) +DNL ₂)·ΔV ₂+(4C _(x) +DNL ₃)·ΔV₃  (Equation 1)

[0024] Differential non-linearities in the A to D converter are measuredusing a standard technique. The differential non-linearities associatedwith each of the bits is then taken as known, hence, DNL₁, DNL₂, andDNL₃ are all known in equation (1) Then, since Q=CΔV, V₁, V₂, and V₃ canbe calculated and stored as compensation values.

[0025] The compensation values are stored in programmable element 208which can be, for example, fusible links or a memory. These values areused to drive the respective D/A converters which are preferably locatedon the same semiconductor substrate along with the A/D converter 100,and the capacitors C1 through C3. Each of the D/A converters 206, 212,and 214 produces a respective output. The DAC1 produces output 210 whichrepresents the voltage value V₁. Similarly, DAC2 produces an output V₂and DAC3 produces an output V₃. Effectively this changes the ΔVassociated with the capacitor in a way which compensates for therespective non-linearity.

[0026] As described above, this solution, unlike other solutions,corrects the analog part of the analog to digital converter circuit.

[0027] A solution which is even more analog is shown in FIG. 3. FIG. 3shows the same basic capacitor and A/D converter setup. However, in FIG.3, a voltage V_(X) is provided biasing three potentiometers 300, 302,304. These potentiometers are set to a position where they will producethe desired output. For example, the potentiometer 300 is set to producethe voltage V₁, the potentiometer 302 is set to produce the voltage V₂,and the potentiometer 304 is set to produce the voltage V₃. Thiseffectively carries out a totally analog solution to the problem,without requiring any on-chip digital circuitry.

[0028] Yet another totally analog solution is shown in FIG. 4. In thissolution, the bias voltage V_(X) biases a resistive ladder 400. Tapsbetween the various resistances are attached to the respective activeterminals, e.g., terminal 200. The voltage divider and taps are set suchthat the appropriate bias voltages V₁, V₂, V₃ are supplied to theappropriate pins.

[0029] Although only a few embodiments have been disclosed in detailabove, those of skill in the art will certainly understand thatmodifications are possible in these embodiments while still maintainingwithin the teaching of the present invention and specifically within theclaims.

[0030] For example, the preferred mode teaches the differentialnon-linearity-corrected total charge which is a reference for an A/Dconverter. However, the charge on line 200 could be used to drive anysimilar device which requires scaled charge. Other analog digitalsystems could be used to produce the DNL-corrective voltages V₁, V₂, V₃.In addition, while an example of 3-bits is given, it should beunderstood that this same system could be used to correct 1 bit, 2 bits,or any number of bits. This system could be used to correct all bits ofA/D converter, or only some bits of the A/D converter. This same conceptcould also be used to correct a D/A converter.

[0031] While the preferred mode describes changing one of the switchedvalues on the capacitor, either one or both could be changed.

[0032] All of these modifications are intended to be encompassed withinthe claims, in which:

What is claimed is:
 1. A compensated analog-to-digital converter system,comprising: an analog-to-digital converter module, of a type whichrelies on scaled capacitors to determine an output value; an array ofscaled capacitors including first, second and third capacitors, a commonline connected commonly to one end of each of the capacitors, aplurality of switched connections, each connected to a second end of oneof the capacitors, and configured for switching the second end of saideach capacitors between a first potential and a second potential whichis different than the first potential; and a voltage source forproducing a first voltage for said first potential of said firstcapacitor, and for producing a second voltage for said first potentialof a second capacitor, said second voltage being different than saidfirst voltage and for producing a third voltage for said first potentialof a third capacitor, said third voltage being different than said firstand second voltages.
 2. A system as in claim 1 wherein said firstpotential is a voltage, said second potential is ground, and a firstvoltage of the first potential that is connectable to the firstcapacitor is different than a second voltage of a first potential whichis connected to the second capacitor.
 3. A system as in claim 2 whereineach voltage forming the first potential that is connected to one ofsaid capacitors is different than a first potential which is connectedto each other one of said capacitors.
 4. A system as in claim 1, whereinsaid analog to digital converter system is an N bit system, and whereineach of said N bits includes separate capacitor parts associatedtherewith, each of said separate capacitor parts having a firstpotential which is different than a first potential applied to eachother of said capacitor parts.
 5. A system as in claim 1, furthercomprising a plurality of separate voltage sources, each of saidseparate voltage sources connected directly to one of said capacitorparts.
 6. A system as in claim 5, wherein said separate voltage sourcescomprise D/A converters.
 7. A system as in claim 6, wherein said D/Aconverters are responsive to values in a respective memory.
 8. A systemas in claim 1, further comprising a resistive ladder for producing saidplurality of voltages.
 9. A system as in claim 1, further comprising avoltage source, and a plurality of variable resistors, each respectivelyconnected to said voltage source to produce said plurality of voltages.10. A system, comprising: an analog-to-digital converter module, of atype which relies on capacitors which have different values to determinean output digital value, said analog to digital converter moduleincluding a plurality of capacitors, with at least one capacitor foreach of a plurality of bits, each of said at least one capacitors havinga different capacitive value; and a plurality of correction elements,respectively connected to some of said plurality of capacitors forproviding correction values for compensating for inaccuracies in saiddifferent capacitive values, each of said correction elements configuredto produce a different output voltage, each of which different outputvoltages is coupled to a respective capacitor to be used to correct forsaid inaccuracies in said capacitors.
 11. A system as in claim 10,wherein each of said plurality of correction values is digitallycontrollable by application of a digital signal thereto.
 12. A system asin claim 11, wherein each of said plurality of correction elementsincludes a D/A converter for receiving said digital signal and producingan analog voltage output responsive thereto, said analog voltage to beused as said correction value.
 13. A system as in claim 10, wherein saidcorrection elements include resistors, forming separate voltages from acommon voltage source.
 14. A system as in claim 13, wherein saidresistors are arranged in a ladder arrangement.
 15. A system as in claim13, wherein said resistors are variable resistors.
 16. A system,comprising: an analog-to-Digital converter module, of a type whichrelies on capacitors which have different values to determine an outputdigital value, said analog to digital converter module including aplurality of capacitors, with at least one capacitor for each of aplurality of bits, each of said at least one capacitors having atdifferent capacitive value; and a plurality of correction elements,respectively connected to some of said plurality of said capacitors, andeach formed of a digital to analog converter for receiving said outputdigital value which is related to a correction for inaccuracies in saidcapacitive values, and said digital to analog converter producing ananalog output voltage, connected to the respective capacitor, and usedto correct for said inaccuracies.
 17. A system as in claim 16, whereinsaid analog to digital converter module is an N bit module, with said atleast one capacitor that is associated with each of said plurality ofbits having a respective one of said correction elements connectedthereto.